`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:16:30 11/29/2011
// Design Name:   PongGame
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/Cs3710/16bitcpu/PongGame_simulation.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: PongGame
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module PongGame_simulation;

	// Inputs
	reg clk;
	reg invert;
	reg SW0;
	reg SW1;
	reg SW2;
	reg data;
	reg data2;

	// Outputs
	wire vga_h_sync;
	wire vga_v_sync;
	wire [2:0] R;
	wire [2:0] G;
	wire [1:0] B;
	wire latch;
	wire latch2;
	wire pulse;
	wire pulse2;
	wire [11:8] SF_D;
	wire LCD_E;
	wire LCD_RS;
	wire LCD_RW;
	wire [11:0] plyr_input;
	reg reset;

	// Instantiate the Unit Under Test (UUT)
	PongGame uut (
		.clk(clk), 
		.reset(reset),
		.invert(invert), 
		.vga_h_sync(vga_h_sync), 
		.vga_v_sync(vga_v_sync), 
		.R(R), 
		.G(G), 
		.B(B), 
		.SW0(SW0), 
		.SW1(SW1), 
		.SW2(SW2), 
		.latch(latch), 
		.latch2(latch2), 
		.pulse(pulse), 
		.pulse2(pulse2), 
		.data(data), 
		.data2(data2), 
		.SF_D(SF_D), 
		.LCD_E(LCD_E), 
		.LCD_RS(LCD_RS), 
		.LCD_RW(LCD_RW), 
		.plyr_input(plyr_input)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		invert = 0;
		SW0 = 0;
		SW1 = 0;
		SW2 = 0;
		data = 0;
		data2 = 0;
		reset = 0;
		#1;
		reset = 1;
		// Wait 100 ns for global reset to finish
		#100;
		reset = 0;
        
		// Add stimulus here

	end

always begin
#5; 
clk=~clk;
end
      
endmodule

